5-stage pipelined RISC-V core in SystemVerilog
A working RISC-V processor from the instruction set up, with the hazard and forwarding logic that keeps five instructions in flight at once without breaking correctness.
Overview
A 5-stage pipelined RISC-V processor built in SystemVerilog: Fetch, Decode, Execute, Memory, Writeback. Pipelining runs instructions in parallel, which is fast but creates hazards when one instruction needs a result another hasn't produced yet. I implemented forwarding and hazard-detection logic to resolve those, and verified the datapath cycle-accurately against test programs in QuestaSim.
Fetch, Decode, Execute, Memory, Writeback, each running a different instruction every cycle.
Logic that spots data and control dependencies and stalls only when it has to.
Routes results straight between stages so dependent instructions don't wait on the register file.
Cycle-accurate checks against test programs in QuestaSim, plus a pipeline visualizer.